1. Field of Invention
This invention relates to flash memory and in particular to creating a reference by which to read the state of flash memory cells.
2. Description of Related Art
Reading data from a flash memory cell requires some method of determining whether the signal produced by the cell on a bit line is a logical "1" or a logical "0". A common method is to use a differential sense amplifier in which a reference is connected to one input leg of the amplifier. In some cases the sense amplifier compares a bit line voltage to a DC reference voltage. This sensing method is slow because time must be allotted to allow the bit line to settle. Other schemes use a dynamic sensing method in which a reference current is used. In the dynamic sensing scheme a half current is set up to detect between a "0" state and a "1" state. One of the challenges is to design a reference circuit which produces an output current that with tracks the memory cells for which it is used to read. Also memory cells are connected to bit lines and the capacitive loading effects of the bit lines needs to be matched by die reference circuit to produce similar performance between the memory cells and die reference circuits.
In U.S. Pat. No. 5,771,192 (Kim et al.) a two transistor reference circuit provides a reference voltage for reading a flash memory cell through an unused bit line to a page buffer that includes a pair of cross coupled buffers. One of the two transistors acts as a gate and the other as the reference voltage source. This invention compares the bit line voltage of a memory cell being read to the bit line voltage of the reference circuit to determine the value of the data being read. This invention does not disclose a current sensing scheme nor an application for a multi-bit flash memory application. U.S. Pat. No. 5,754,475 (Bill et al.) describes a reference scheme for a multi-bit flash memory in which multiple reference cells are arranged in rows and columns. The number of rows corresponds to the number of rows in the flash memory and the number of columns depends on the number of bits in the multi-bit memory cells.
In U.S. Pat. No. 5,638,326 (Hollmer et al.) a flash memory read and verify circuit is disclosed that minimizes by design the effects of process, power and temperature variations. The read and verify circuit uses a bias circuit with a cascode transistor for the reference. In U.S. Pat. No. 5,629,892 (Tang) a flash memory is described where an array of reference cells is separate from the array of memory cells. The transconductance of the reference cells is matched to the transconductance of the memory cells to produce a reference current. In U.S. Pat. No. 5,596,527 (Tomioka et al.) is described a multi-bit flash memory with multiple reference cells providing a multiple of threshold voltages. The reference cells are made up from memory cells, and the multiple reference cells associated with a word line of memory cells are accessed using the same wordline as used for the memory cells. In U.S. Pat. No. 5,544,116 (Chao et al.) a program and erase verify circuit is disclosed in which different voltages are supplied to the memory and reference cells to read the program and erase verify conditions. In U.S. Pat. No. 5,172,338 (Mehrotra et al.) a set of reference cells which closely track the multi-bit flash memory cells are used for read and erase verification.
There are many approaches to reading flash memory cell data. Those approaches that utilize a differential sense amplifier use a reference cell to generate a reference voltage or current to compare with the bit line signal. In DC sensing schemes the bit line needs to settle before a comparison is made to a reference voltage. The need to allow settling time makes the operation slow, and therefore a dynamic sensing scheme where the sense amplifier uses a current reference is more advantageous. In dynamic read sensing a half current is often used which is generated/ from a reference circuit that tracks with the memory cell and has a threshold voltage which is half that of the memory cell. The half threshold voltage of the reference cell produces a reference current that is half the current between a logical "0" and a logical "1" of the memory cell. One of the challenges is how to build a reference circuit that tracks with the memory cell current changes with respect to process, temperature and power supply variations. Another problem is the capacitive loading of bit lines that slows the bit line voltage response and the comparison process. This is particularly important if voltage sensing is used. Turning on the memory cell and the reference cell at the same time is important to minimize settling errors. Better margin due to better cell tracking and load matching permits faster dynamic sensing.
In addition to the normal read operation, flash memory has two other read type operations, called "program Verify" and "erase verify", in which the memory cell threshold is compared to thresholds that are higher and lower than the half threshold reference. For simplicity of circuit design, it would be useful to incorporate capability to sense all the different reference levels within a single unit.